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HM5212325FBPC-B60
128M LVTTL interface SDRAM 100 MHz 1-Mword x 32-bit x 4-bank PC/100 SDRAM
ADE-203-1122C (Z) Rev. 1.0 May. 12 , 2000 Description
The Hitachi HM5212325FBPC is a 128-Mbit SDRAM organized as 1048576-word x 32-bit x 4-bank. All inputs and outputs are referred to the rising edge of the clock input. It is packaged in standard 90-bump fine pitch BGA.
Features
* * * * * * * * * Single chip wide bit solution (x 32) 3.3 V power supply Clock frequency: 100 MHz (max) LVTTL interface Extremely small foot print: 0.8 mm pitch Package: FBGA (BP-90) 4 banks can operate simultaneously and independently Burst read/write operation and burst read/single write operation capability Programmable burst length: 4/8/full page 2 variations of burst sequence Sequential (BL = 4/8/full page) Interleave (BL = 4/8) Programmable CAS latency: 2/3 Byte control by DQMB Refresh cycles: 4096 refresh cycles/64 ms
* * *
HM5212325FBPC-B60
* 2 variations of refresh Auto refresh Self refresh * Full page burst length capability Sequential burst Burst stop capability
Ordering Information
Type No. HM5212325FBPC-B60* Frequency 100 MHz CAS latency 3 Package 10 mm x 13 mm 90 bump FBGA (BP-90)
Note: 66 MHz operation at CAS latency = 2.
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HM5212325FBPC-B60
Pin Arrangement
90-bump FBGA
1 A B C D E F G H J K L M N P Q
VSS
2
DQ15
3
VSS
6
VCC
7
DQ0
8
VCC
DQ14
DQ13
VCC
VSS
DQ2
DQ1
DQ12
DQ11
VSS
VCC
DQ4
DQ3
DQ10
DQ9
VCC
VSS
DQ6
DQ5
DQ8 DQ MB1 NC
NC
VSS
VCC
NC
DQ7 DQ MB0 RAS
Open
NC
CAS
WE
CKE
CLK
NC
CS
A11
A9
A8
A12
NC
NC
A5 DQ MB3 DQ31
A6
A7
A13
A10
A0 DQ MB2 DQ16
A3
A4
A1
A2
NC
VSS
VCC
NC
DQ29
DQ30
VCC
VSS
DQ17
DQ18
DQ27
DQ28
VSS
VCC
DQ19
DQ20
DQ25
DQ26
VCC
VSS
DQ21
DQ22
VSS
DQ24
VSS
VCC
DQ23
VCC
(Top view)
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HM5212325FBPC-B60
Pin Description
Pin name A0 to A13 Function Address input Row address Column address A0 to A11 A0 to A7
Bank select address A12/A13 (BS) DQ0 to DQ31 CS RAS CAS WE DQMB0 to DQMB3 CLK CKE VCC VSS Open Note: Data-input/output Chip select Row address strobe command Column address strobe command Write enable Byte data mask* 1 Clock input Clock enable Power supply Ground Open* 2 1. DQMB0: DQ0 to DQ7 DQMB1: DQ8 to DQ15 DQMB2: DQ16 to DQ23 DQMB3: DQ24 to DQ31 2. Don't connect. Internally connected with die.
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HM5212325FBPC-B60
Block Diagram
14
A0 to A13 CS RAS CAS WE CLK CKE
64-Mbit SDRAM 4M x 16
64-Mbit SDRAM 4M x 16
4 DQMB 0 to DQMB 3 32 DQ 0 to DQ 31
2
16
2
16
Power-up Sequence and Initialization Sequence
Power up sequence 100 s VCC CKE, DQMB CLK CS, DQ 0V Low Low Low
Power stabilize
Initialization sequence 200 s
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HM5212325FBPC-B60
Absolute Maximum Ratings
Parameter Voltage on any pin relative to V SS Supply voltage relative to VSS Short circuit output current Operating temperature Storage temperature Note: 1. Respect to V SS . Symbol VT VCC Iout Topr Tstg Value -0.5 to VCC + 0.5 ( 4.6 (max)) -0.5 to +4.6 50 0 to +70 (Tj max = 110) -55 to +125 Unit V V mA C C Note 1 1
DC Operating Conditions (Tcase = 0 to +70C [Tj max = 110C])
Parameter Supply voltage Symbol VCC VSS Input high voltage Input low voltage Notes: 1. 2. 3. 4. 5. VIH VIL Min 3.0 0 2.0 -0.3 Max 3.6 0 VCC + 0.3 0.8 Unit V V V V Notes 1, 2 3 1, 4 1, 5
All voltage referred to VSS . The supply voltage with all VCC pins must be on the same level. The supply voltage with all VSS pins must be on the same level. VIH (max) = VCC + 2.0 V for pulse width 3 ns at VCC. VIL (min) = VSS - 2.0 V for pulse width 3 ns at VSS .
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HM5212325FBPC-B60
DC Characteristics (Tcase = 0 to +70C [Tj max = 110C]), VCC = 3.3 V 0.3 V, VSS = 0 V)
HM5212325F -B60 Parameter Operating current (CAS latency = 2) (CAS latency = 3) Standby current in power down Standby current in power down (input signal stable) Standby current in non power down Standby current in non power down (input signal stable) Active standby current in power down Active standby current in power down (input signal stable) Active standby current in non power down Active standby current in non power down (input signal stable) Burst operating current (CAS latency = 2) (CAS latency = 3) Refresh current Self refresh current Self refresh current (L-version) Input leakage current Output leakage current Output high voltage Output low voltage Symbol I CC1 I CC1 I CC2P I CC2PS I CC2N I CC2NS I CC3P I CC3PS I CC3N I CC3NS Min -- -- -- -- -- -- -- -- -- -- Max 100 110 6 4 32 18 8 6 40 30 Unit mA mA mA mA mA mA mA mA mA mA CKE = VIL, t CK = 12 ns CKE = VIL, t CK = CKE, CS = VIH, t CK = 12 ns CKE = VIH, t CK = CKE = VIL, t CK = 12 ns CKE = VIL, t CK = CKE, CS = VIH, t CK = 12 ns CKE = VIH, t CK = 6 7 4 9 1, 2, 6 2, 7 1, 2, 4 2, 9 Test conditions Burst length = 1 t RC = min Notes 1, 2, 3
I CC4 I CC4 I CC5 I CC6 I CC6 I LI I LO VOH VOL
-- -- -- -- -- -2 -3 2.4 --
110 135 190 2 0.8 2 3 -- 0.4
mA mA mA mA mA A A V V
t CK = min, BL = 4
1, 2, 5
t RC = min VIH VCC - 0.2 V VIL 0.2 V 0 Vin VCC 0 Vout VCC DQ = disable I OH = -4 mA I OL = 4 mA
3 8
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HM5212325FBPC-B60
Notes: 1. I CC depends on output load condition when the device is selected. ICC (max) is specified at the output open condition. 2. One bank operation. 3. Input signals are changed once per one clock. 4. Input signals are changed once per two clocks. 5. Input signals are changed once per four clocks. 6. After power down mode, CLK operating current. 7. After power down mode, no CLK operating current. 8. After self refresh mode set, self refresh current. 9. Input signals are V IH or VIL fixed.
Capacitance (Ta = 25C, VCC = 3.3 V 0.3 V)
Parameter Input capacitance (CLK) Input capacitance (Input except DQM) Input capacitance (DQM) Output capacitance (DQ) Notes: 1. 2. 3. 4. Symbol CI1 CI2 CI3 CO Min 4 4 2 2 Max 8 8 5 5 Unit pF pF pF pF Notes 1, 2, 4 1, 2, 4 1, 2, 4 1, 2, 3, 4
Capacitance measured with Boonton Meter or effective capacitance measuring method. Measurement condition: f = 1 MHz, 1.4 V bias, 200 mV swing. DQMB = VIH to disable Dout. This parameter is sampled and not 100% tested.
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HM5212325FBPC-B60
AC Characteristics (Tcase = 0 to +70C [Tj max = 110C]), VCC = 3.3 V 0.3 V, VSS = 0 V)
HM5212325F -B60 Parameter System clock cycle time (CAS latency = 2) (CAS latency = 3) CLK high pulse width CLK low pulse width Access time from CLK (CAS latency = 2) (CAS latency = 3) Data-out hold time CLK to Data-out low impedance CLK to Data-out high impedance Input setup time CKE setup time for power down exit Input hold time HITACHI Symbol t CK t CK t CKH t CKL t AC t AC t OH t LZ t HZ t AS , t CS, t DS, Tsi t CES t CESP Tpde PC/100 Symbol Tclk Tclk Tch Tcl Tac Tac Toh Min 15 10 3 3 -- -- 3 2 -- 2 2 1 70 50 20 20 10 20 1 -- Max -- -- -- -- 8 6 -- -- 6 -- -- -- -- 120000 -- -- -- -- 5 64 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms 1, 2 1, 2, 3 1, 4 1, 5, 6 1 1, 5 1 1 1 1 1 1 1 1 1, 2 Notes 1
t AH, t CH, t DH, Thi t CEH Trc Tras Trcd Trp Tdpl Trrd
Ref/Active to Ref/Active command t RC period Active to Precharge command period Active command to column command (same bank) Precharge to active command period Write recovery or data-in to precharge lead time Active (a) to Active (b) command period Transition time (rise and fall) Refresh period t RAS t RCD t RP t DPL t RRD tT t REF
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HM5212325FBPC-B60
Notes: 1. 2. 3. 4. 5. 6. AC measurement assumes t T = 1 ns. Reference level for timing of input signals is 1.5 V. Access time is measured at 1.5 V. Load condition is CL = 50 pF. t LZ (min) defines the time at which the outputs achieves the low impedance state. t HZ (max) defines the time at which the outputs achieves the high impedance state. t CES define CKE setup time to CLK rising edge except power down exit command. t AS /tAH: Address, tCS/tCH: CS, RAS, CAS, WE, DQM. t DS/tDH: Data-in, tCES/tCEH: CKE
Test Conditions * Input and output timing reference levels: 1.5 V * Input waveform and output load: See following figures
2.4 V
input
0.4 V
2.0 V 0.8 V
I/O CL t
T
tT
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HM5212325FBPC-B60
Package Dimensions
HM5212325FBPC (BP-90)
Unit: mm
0.20 C B
0.15
A -C0.8 A
10.0
4x
0.20 C A 0.20 C
Index
11.2
0.8 B 2.4 5.6 90 x 0.45 0.05 0.08 M C A B Details of the part A BP-90 -- -- 0.28 g
12.8 0.10
13.0
9.8 0.10
0.41 - 0.16
+ 0.04
1.45 Max
Hitachi Code JEDEC EIAJ Mass (reference value)
0.12 C
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HM5212325FBPC-B60
Cautions
1. Hitachi neither warrants nor grants licenses of any rights of Hitachi's or any third party's patent, copyright, trademark, or other intellectual property rights for information contained in this document. Hitachi bears no responsibility for problems that may arise with third party's rights, including intellectual property rights, in connection with use of the information contained in this document. 2. Products and product specifications may be subject to change without notice. Confirm that you have received the latest product standards or specifications before final design, purchase or use. 3. Hitachi makes every attempt to ensure that its products are of high quality and reliability. However, contact Hitachi's sales office before using the product in an application that demands especially high quality and reliability or where its failure or malfunction may directly threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment or medical equipment for life support. 4. Design your application so that the product is used within the ranges guaranteed by Hitachi particularly for maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions and other characteristics. Hitachi bears no responsibility for failure or damage when used beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so that the equipment incorporating Hitachi product does not cause bodily injury, fire or other consequential damage due to operation of the Hitachi product. 5. This product is not designed to be radiation resistant. 6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without written approval from Hitachi. 7. Contact Hitachi's sales office for any questions regarding this document or Hitachi semiconductor products.
Hitachi, Ltd.
Semiconductor & Integrated Circuits. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan Tel: Tokyo (03) 3270-2111 Fax: (03) 3270-5109
URL
NorthAmerica : http:semiconductor.hitachi.com/ Europe : http://www.hitachi-eu.com/hel/ecg Asia (Singapore) : http://www.has.hitachi.com.sg/grp3/sicd/index.htm Asia (Taiwan) : http://www.hitachi.com.tw/E/Product/SICD_Frame.htm Asia (HongKong) : http://www.hitachi.com.hk/eng/bo/grp3/index.htm Japan : http://www.hitachi.co.jp/Sicd/index.htm For further information write to:
Hitachi Europe GmbH Electronic components Group Dornacher Strae 3 D-85622 Feldkirchen, Munich Germany Tel: <49> (89) 9 9180-0 Fax: <49> (89) 9 29 30 00 Hitachi Europe Ltd. Electronic Components Group. Whitebrook Park Lower Cookham Road Maidenhead Berkshire SL6 8YA, United Kingdom Tel: <44> (1628) 585000 Fax: <44> (1628) 778322 Hitachi Asia Pte. Ltd. 16 Collyer Quay #20-00 Hitachi Tower Singapore 049318 Tel: 535-2100 Fax: 535-1533 Hitachi Asia Ltd. Taipei Branch Office 3F, Hung Kuo Building. No.167, Tun-Hwa North Road, Taipei (105) Tel: <886> (2) 2718-3666 Fax: <886> (2) 2718-8180 Hitachi Asia (Hong Kong) Ltd. Group III (Electronic Components) 7/F., North Tower, World Finance Centre, Harbour City, Canton Road, Tsim Sha Tsui, Kowloon, Hong Kong Tel: <852> (2) 735 9218 Fax: <852> (2) 730 0281 Telex: 40815 HITEC HX
Hitachi Semiconductor (America) Inc. 179 East Tasman Drive, San Jose,CA 95134 Tel: <1> (408) 433-1990 Fax: <1>(408) 433-0223
Copyright (c) Hitachi, Ltd., 1998. All rights reserved. Printed in Japan.
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HM5212325FBPC-B60
Revision Record
Rev. 0.0 0.1 Date Contents of Modification Drawn by S. Hatano Y. Kagaya Approved by S. Hatano S. Hatano Oct. 25, 1999 Initial issue Jan. 7, 2000 Correct errors of pin arrangement Correct errors of DC Characteristics I LI: -4/4 to -2/2 A I LO : -6/6 to -3/3 A Package dimension Change tolerance value 0.2 Feb. 29, 2000 Capacitance CI1 min: 5 pF to 4 pF CI2 min: 5 pF to 4 pF CI3 min: 2.5 pF to 2 pF CO min: 3 pF to 2 pF May. 12 ,2000 Package dimension Change of seated height M. Nishimura I. Hihara
1.0
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